1. Field of the Invention
The present invention relates to a redundancy circuit which is used in a semiconductor memory device to prevent a defective memory medium from interfering with operation of the semiconductor memory device. In particular, the present invention relates to a technique for obtaining a smaller and faster redundancy-circuit equipped with semiconductor memory device.
2. Description of the Prior Art
In most cases, when a semiconductor memory device includes one or two defective memory cells in a memory cell array, i.e., if there is defect of a few bits, the semiconductor memory device becomes defective. Even with defect of a few bits, a semiconductor memory device is labelled as a substandard product. A semiconductor memory device having redundancy is a semiconductor memory device which comprises a redundancy circuit which compensates for defect of a few bits.
FIG. 9 is a block diagram of a conventional semiconductor memory device. In FIG. 9, indicated at numerical reference 1 is a data input terminal for receiving data which is to be stored D.sub.in, indicated at 2 is a write signal input terminal for receiving a write enable signal WE under the control of which data is written and read, and indicated at 3 is a data output terminal for outputting stored data D.sub.out. Indicated at 4 is an address signal input terminal for receiving an address signal AD which designates the address of a memory location which is specified by a row and a column of the inputted data D.sub.in and the stored data to be outputted D.sub.out. Indicated at 5 is a memory cell array housing arrays of memory cells for storing the data D.sub.in which has been stored at an address which is specified with a row and a column by the address signal AD and for outputting the stored data D.sub.out. Indicated at 6 is a row decoder which is connected to the address signal input terminal 4 and which double signs a row address signal of a address signal AD received therein in order to designate the row of an address. At reference number 7 word lines are indicated which are connected to the row decoder 6 and the memory cells of the memory array 5 so as to transfer a signal which controls the memory cells. At reference number 8, a defective row address signal generation circuit is shown which includes a plurality of fuses. By blowing the fuses with a laser or the like, the defective row address signal generation circuit 8 generates a row address signal which tells which row includes a defective memory cell. Indicated at 9 is a defective row address signal detection circuit which is connected to the defective row address signal generation circuit 8 and the address signal input terminal 4. The defective row address signal detection circuit 9 judges whether a row address signal received therein coincides with the defective row address signal and designates a spare row if the two signals coincide with each other. Indicated at 10 is a spare word line connected to both spare row memory cells and the defective row address signal detection circuit 9 and which transmits a signal which controls the spare memory cells. At numerical reference 11 are indicated fuses which are provided in the word lines 7 and the spare word line 10. The fuses 11 are to be blown to prohibit transfer of the control signal from the row decoder 6 or the defective row address signal detection circuit 9 to the memory cells or the spare memory cells. Indicated at 12 is a column decoder which is connected to the address signal input terminal 4 and which double signs a column address signal of an address signal AD received therein in order to designate the column of an address. Indicated at 14 is a column selector connected to the column decoder 12. In response to a signal received from the column decoder 12, the column selector 14 selects a bit line 13 to attain data transfer between the data input terminal 1 and the selected bit line 13 or between the data output terminal 3 and the selected bit line 13. The bit lines 13 are connected to the memory cells of the memory cell array 5 to transmit the data D.sub.in or the data D.sub.out to the memory cells. Indicated at 15 is a defective column address signal generation circuit which includes a plurality of fuses. By blowing the fuses with a laser or the like, the defective column address signal generation circuit 15 generates a column address signal which tells which column includes a defective memory cell. Indicated at 16 is a defective column address signal detection circuit which is connected to the defective column address signal generation circuit 15 and the address signal input terminal 4. The defective column address signal detection circuit 16 judges whether a column address signal received therein coincides with the defective column address signal and designates a spare column if the two signals coincide with each other. Indicated at 17 is a spare bit line which is connected to spare column memory cells and the column selector 14. The spare bit line 17 attains transfer of the data D.sub.in which is to be stored in the spare memory cells or the data D.sub.out which is to be read from the spare memory cells. At numerical reference 18 fuses are indicated which are provided in the bit lines 13 and the spare bit line 17. The fuses 18 are to be blown to disconnect the column selector 14 from the memory cells or the spare memory cells so that the data D.sub.in or the data D.sub.out would not be transferred. A semiconductor memory device is indicated at numerical reference 20a.
Next, description will be given on the state of a semiconductor memory device 20a where there is no defective memory cell in the memory cell array 5. When the memory cell array 5 does not include a defective memory cell, the fuses 11 of the spare word line 10 and the fuses 18 of the spare bit line 17 are blown, consequently preventing the control signal from routed from the defective row address signal detection circuit 9 to the memory cells of the spare row through the spare word line 10. At the same time, the spare bit line 17 is prevented from selected by the defective column address signal detection circuit 16. Hence, only the memory cell which is addressed by the row decoder 6 and the column decoder 12 will be effective.
Now, description will be given on the state of the semiconductor memory device 20a where the memory cell of the row a and the column b of the memory cell array 5 is found defective in a test step. When the memory cell array 5 thus includes a defective memory cell, two methods remain open to protect the semiconductor memory device 20a against the defect.
The first method is "bit line remedy method." In the bit line remedy method, the fuse 18 on the bit line 13 of the column b and the fuse 11 provided on the spare word line 10 are blown. Next, the fuses in the defective column address signal generation circuit 15 are blown such that the defective column address signal generation circuit 15 generates a column address signal which designates the column b. Once set as above, the semiconductor memory device 20a demands that, for example, when the column address signal included in the address signal AD received from the address signal input terminal 4 designates not the column b but a column n, the column decoder 12 outputs a signal which designates the column n to the column selector 14 and that the defective column address signal detection circuit 16 finds that the column n does not coincide with the column b and outputs a signal which calls for deselection of the spare bit line 17. Thus, the column selector 14 selects only the bit line 13 of the column n so that the memory cell connected to the column n becomes accessible.
Where the semiconductor memory device is set as above, when the address signal AD inputted at the address signal input terminal 4 includes a column address signal which designates the column b, the column decoder 12 provides with the column selector 14 a signal which designates the column b while the defective column address signal detection circuit 16, detecting that there is coincidence at the column b between the column address signal received from the address signal input terminal 4 and the column address signal outputted by the defective column address signal generation circuit 15, outputs to the column selector 14 a signal which demands the column selector 14 to select the spare bit line 17. The column selector 14 then selects both the bit line 13 of the column b and the spare bit line 17 on the column b at the same time. However, since the fuse 18 provided on the bit line 13 of the column b is blown, the memory cell connected to the bit line 13 of the column b is not accessed and instead the memory cell connected to the spare bit line 17 is accessed. Thus, by using the spare memory cell which is connected to the spare bit line 17 instead of the defective memory cell which is connected to the bit line 13 and the column b, the semiconductor memory device 20a is prevented from becoming defective due to the internal defective memory cell.
The second method is "word line remedy method." In this method, the fuse 11 provided on the word line 7 of the row a and the fuse 18 provided on the spare bit line 17 are blown. Likewise in the bit line remedy method, by using the spare word line 10 instead of the word line 7 of the row a connected to the defective memory cell, the semiconductor memory device 20 is protected against the defective memory cell.
Having such a construction, the conventional semiconductor memory device needs a line-basis remedy method in which a row as a whole or a column as a whole has to be replaced to replace a single defective memory cell with a spare memory cell. A semiconductor memory device having a memory capacity of 256K bits can be cited as an example. Suppose that the semiconductor memory device is organized as a 8-bit, 4-column/bit, 16-block memory device, the total bit lines are 512 (8.times.4.times.16) and the total spare bit lines are 128 (8.times.16). Hence, the semiconductor memory device would not comprise redundancy unless the arrays of the memory cells increase in number from 512 to 640, in which case due to the expanded space for the increased memory cell arrays, the chip will become large.
In addition, a delay through the defective row address signal detection circuit 9 or the defective column address signal detection circuit 16 is added to the access time necessary for accessing a spare memory cell instead of a defective memory cell. Thus, accessing of the row or the column of the address of a defective memory cell takes a long time, decelerating the operation speed of the semiconductor memory device.
There is still other problem which relates to incorporation of the redundancy-circuit equipped semiconductor memory device in an application-oriented semiconductor integrated circuit (ASIC). Since the coordinates on which the semiconductor memory device is to be placed are different in different ASICs, and since the number and the locations of the fuses 11 and 18 which are provided in the word lines 7 and 10 and in the bit lines 13 and 17 are different depending on standards of the semiconductor memory device, and further since so are the number and the locations of the fuses of the defective row address signal generation circuit 8 and the defective column address signal generation circuit 15, the locations of the fuses need to be entered and stored in a fuse trimming apparatus for each ASIC. This adversely affects productivity of mass production of the semiconductor memory devices which are to be built in ASICs.